Manil Gomony
Application Specific Integrated Circuit Lab
CMOS scaling is approaching its physical limit and processing demands are ever increasing. Our aim is to design cross-stack optimizations to push the boundaries of what is physically possible.
![[Translate to English:]](https://assets.w3.tue.nl/w/fileadmin/_processed_/7/4/csm_Visual%20ASIC%20Lab_e5e96b7928.jpg "[Translate to English:]")
Research Profile
CMOS scaling is approaching its physical limit and processing demands are ever increasing. To keep the energy consumption and silicon area usage within the budget, the ASIC lab focuses its research on optimizations at different levels of design stack from applications, architecture, micro-architecture, logic, circuit, device and technology.
Meet some of our Researchers
Recent Publications
Our most recent peer reviewed publications
-
Floran de Putter,M.D. Gomony,Pekka Jääskeläinen,Henk Corporaal
BrainTTA
(2023) -
M. Gomony
Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic Model
(2023) -
Manil Dev Gomony,Floran de Putter,Anteneh Gebregiorgis,Gianna Paulin,Linyan Mei,Vikram Jain,Said Hamdioui,Victor Sanchez,Tobias Grosser,Marc Geilen
PetaOps/W edge-AI µProcessors: Myth or reality?
(2023) -
Emad Ibrahim,Bart van den Dool,Sayandip De,Manil Dev Gomony,Jos A. Huisken,Marc C.W. Geilen
Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications
IEEE Transactions on Circuits and Systems I: Regular Papers (2022)
Contact
-
Visiting address
Flux, room 4.130Groene Loper 195612 AP EindhovenNetherlands -
Postal address
Department of Electrical EngineeringP.O. Box 5135600 MB EindhovenNetherlands -
Teamlead